1. Field of the Invention
The invention relates in general to techniques for manufacturing memory integrated circuits, and more particularly to a planarization method for a self-aligned contact process which can avoid stringer effects that may result in bridging phenomena.
2. Description of the Related Art
A conventional DRAM manufacturing process makes use of a technique called self-aligned contact to reduce the layout area of memory components. FIG. lA to 1C are cross-sectional views showing how, in conventional processing, the definition of a contact window in a self-aligned contact process is carried out. A DRAM component generally consists of a MOS transistor which acts as a switching element, and a capacitor which acts as a charge storage device. Both of these elements are fabricated on a silicon substrate 10. As shown in the drawings, a field oxide layer 11 acts as an insulating structure between separate memory components. A gate dielectric layer 12 is produced by thermal oxidation of the surface of silicon substrate 10 and the gate and the connecting wires, labelled as 13 and 14 respectively, are formed by etching away the same heavily implanted polysilicon layer. Capping oxide layer elements 15 and 16 separately cover the surfaces of the gate 13 and connecting wires 14, respectively. The capping oxide layers 15 and 16 are produced by thermal oxidation of the surface of the polysilicon layer. Source/drain terminals 17 are formed by the implantation of impurities in the silicon substrate 10. Sidewall spacers 18 are laid on opposite sidewalls of the gates 13 and connecting wires 14.
First, as shown in FIG. 1A, a layer of oxide 19 covering the whole surface of the substrate 10 is formed by deposition. Due to the unevenness of the base substrate layer, the surface of the oxide layer 19 also has an undulating profile. Next, a layer of photoresist material 100 is coated on the oxide layer 19, and by a photolithographic technique, the pattern for the contact windows is defined, providing two openings 110 and 120 as shown in FIG. 1B. Then, using the photoresist layer 100 as a mask, the oxide layer 19 is etched to expose the desired contacts to the source/drain terminals 17. Thereafter, the photoresist layer 100 is removed, thereby obtaining the cross-sectional configuration shown in FIG. 1C. Then, the capacitor of the DRAM component may be formed precisely at the points where the contact windows 110 and 120 are situated. Some of the basic steps in the capacitor formation process include first structurally forming the bottom terminal layer of the capacitor, followed by forming the dielectric layer on top of the bottom terminal layer, and then finally forming the top terminal layer on top of the dielectric layer.
Since in the conventional manufacturing process there is no prior planarization treatment before the stage where the bottom terminal layer of the capacitor is formed, generally the substrate surface undulates. This undulation is especially pronounced for regions such as the narrow groove between two connecting wires 14. Therefore it is easy, when etching the defined polysilicon layer to form the top and bottom terminal layers of the capacitor, to pick up stringer effects which lead to bridging phenomena. The conventional method for avoiding such stringer effects is to lengthen the etching time. However, this measure will reduce production efficiency. Further, if an additional flushing step is included in the etching process to avoid stringer effects, the reactive gases used, such as Cl and SF, will diminish the capacitor area.